What AI Can Do for Electronic Design Automation
Internet of Things News
Internet of Things Resources
April 1, 2018
For years, analysts and developers have been saying that artificial intelligence (AI) and electronic design automation (EDA) are a perfect match. EDA problems have high dimensionality, discontinuities, nonlinearities and high-order interactions. What better way to grapple with this level of complexity than to apply a technology that takes past experiences and uses them to predict solutions for similar problems?
In fact, AI has begun to come into its own, making tremendous strides over the past few years. But for all its successes, applications of AI-like machine learning, neural networks and deep learning have been slow to find a place in EDA.
But that’s changing.
Enhancing CMP Modeling
Mentor Graphics has enhanced chemical-mechanical polishing (CMP) modeling by generating accurate post-deposition profiles via machine learning and neural networks.
CMP plays a key role in chip fabrication by leveling the wafer layers. The outcome depends on the materials being polished and the density and shapes of the materials in any given location.
Because many of today’s integrated circuit designs are so tightly packed and scaled down, post-CMP planarity variations can significantly affect the fabrication success. To mitigate any negative effects, chipmakers use CMP modeling to detect potential hotspots as part of their design-for-manufacturing flow.
CMP hotspot analysis looks for areas of the design likely to experience post-CMP defects. Because different materials exhibit different erosion rates in the CMP process, the fab must maintain a constant density balance across the die to prevent bumps and dishing that cause shorts and breaks in the metal interconnects.
To achieve optimal CMP modeling accuracy, the chipmakers must be able to generate high-quality, pre-CMP surface profiles. If these profiles are not accurate, the results of CMP simulations for the post-CMP profile will be compromised. The problem is that building physics-based models for different types of depositions processes—such as high-density plasma CVD and spin-on dielectric—is challenging and isn’t practical for more exotic deposition flows, such as enhanced high-aspect-ratio processes.
To address this problem, the engineers at Mentor used machine-learning algorithms to perform sensitivity analysis of measurement data in the pre-CMP surface profiles. They found that the profile dependency was primarily influenced by the underlying pattern geometries. With this information, the researchers used neural network regression calculations to model the pre-CMP surface profile, using the geometric characteristics of the underlying patterns as input. The neural network would then estimate the pre-CMP profile, which would be used as input for the CMP modeling, improving the accuracy of the overall process.
Making the Right Connections
Tackling a related design issue, NetSpeed Systems introduced Turing, a design product that aims to help chip architects optimize SoC (system-on-chip) interconnects. NetSpeed’s approach marks a break with the past, recognizing that architects can no longer rely solely on their experience and intuition to make interconnect topology and routing decisions.
The rise of heterogeneous systems like SoC requires architectures that must accommodate a daunting degree of complexity. To come up with a sound interconnect strategy, a designer must consider a large array of parameters, including routing constraints, connectivity requirements, protocol dependency, clock characteristics and process characteristics, such as wire delay, bandwidth and latency constraints. The number of dimensions in the design space can easily grow to several hundreds.
To address these issues, NetSpeed has adopted a requirements-driven design flow, where the architect specifies IP blocks, connectivity and performance requirements, and system-centric use cases. Turing then uses supervised learning algorithms to search for patterns in interconnect design data to identify promising strategies, evaluating each approach for performance, power and functional safety. The algorithms then suggest an interconnect implementation, allowing the architect to review automatically generated results and fine-tune the implementations accordingly.
These two examples demonstrate how AI has begun to carve out a place in the chip design process, in some cases promising a tenfold improvement in productivity. AI’s ability to complement EDA is no longer in question, the working relationship between the two technologies is a long way from being defined.
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